Today's consumers and original equipment manufacturers require high quality and reliability as a starting point for automotive products, particularly electronics. The electronic component content in automobiles is growing at an estimated 8.1% Compounded Average Annual Growth Rate [Automotive Semiconductor Demand 2005 -2014, Strategy Analytics, Chris Webber, October 2007]. This expansion is driving an ever increasing need for zero defects at product introduction. The challenge for semiconductor suppliers is to meet this requirement while still providing a cost-competitive product.
In this article, the focus will be on best practices for zero defects during the semiconductor product ramp-up to production phase. It is in this early phase of the product life cycle where the probability of shipping parts at risk for early life failures is highest due to newness of the product.
The above figure shows the classic "bathtub" curve illustrating new product reliability over time without implementing any best practices when production begins. Early life failures are considered to be time-zero/low-mileage failures. This rate reduces over time to what is considered a random failure rate (provided any systemic problems have been resolved) based on corrective actions and continual improvement activities being implemented.
As failure rates are reduced to random and the product ages in the field, it begins to reach its rated lifetime leading to an increase in failure rates due to wear out. Typically failure mechanisms that dominate one phase are not necessarily the same mechanisms that dominate other phases of the product life cycle.
The zero defects approach is a focused attack on the "early life" portion of the curve by implementing known best practices. The main strategies deployed for zero defects launch include adequate test-for-quality (TFQ) coverage; special build flow considerations such as burn-in for new technologies; and implementing outlier control. Successful implementation of different strategies in a layered approach, with real time data and device analysis, allows for detection of early life failures, accelerated learning, and timely implementation of corrective actions without impact to the customer.
The first tactic for zero defects during product launch is to implement TFQ best practices. These best practices include VMIN and VMAX testing based on device characterization over temperature and understanding of extreme process conditions (corner lot evaluations); special functional testing very specific to the device design; and other best practices such as power-off leakage testing.
A key aspect of TFQ is setting proper test limits based on statistical data. Additionally, you'll want to ensure that any device design structures that cannot be tested in final package form are tested at wafer probe. A good example is testing oxide-integrity stress in large capacitor structures—if the test and design layout accommodate direct access to the capacitor itself. Other good test implementation practices include those that focus on ensuring high test coverage levels of greater than 95%, scan implementation on high-gate count devices, over-voltage stress testing, and statistically-based quiescent current tests. Combined, these items ensure that the component meets datasheet specifications while screening outlier parts from the product population.
The second tactic deployed in screening-out early life failures is to implement special build flows based on technology risk. An example of such a special flow is implementing burn-in during production ramp. Burn-in is typically implemented with new technologies and custom designs where there is risk in potential pass-through of unknown defects.
To do this properly, you'll need to understand the process technology and design with respect to access of critical components and the conditions selected for burn-in (voltage, temperature, and duration of stress). When deployed effectively, burn-in can accelerate early life failures for better inline detection and defect screening, which drives learning and corrective action loops early in the product's life cycle without negative impact to the customer.
In order to maximize the value of burn-in:
All parts that fail post burn-in testing should be submitted for full electrical and physical failure analysis.
The root cause of each fail signature should be determined.
The appropriate corrective actions should be implemented.
Corrective actions often include defect reduction actions in the wafer fabrication processing technology itself, improvements in automated test equipment stress testing to accelerate fail mechanisms, and improved outlier controls implemented upstream in the process, with the goal to drive post burn-in test results towards 100% yield. The figure below shows an example of improved post burn-in yields after implementing a test enhancement based on what was learned during the production ramp phase.
This plot shows post burn-in yield trend over time and yield increase after test improvements were implemented.
Note that burn-in is an expensive screening tool from an investment perspective when it comes to tooling, equipment, and personnel. Eliminating or reducing burn-in is possible when root cause and corrective actions are verified, and confidence is achieved that results are at target levels.
